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s 6b 071 5 33 com / 1 00 seg driver & controller for stn lcd january . 2000 ver. 4 . 0 prepared by: jae - su, ko ko1942@samsung.co.kr contents in this document are subject to change without notice. no part of this document may be reproduc ed or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 2 s6b0715 specification revi sion history version content date 1.0 cap3p ? c3+, cap2p ? c2+, cap1p ? c1+ cap3m ? c3 - , cap2m ? c2 - , cap1m ? c1 - oscillator frequency f osc ( k hz) = ? 19 (min.): 22.5 (typ.): 26 (max.) f cl ( k hz) = ? 2.37 (min.): 2.81 (typ.): 3.25 (max.) 2.0 temperature coefficien t temps = l: - 0.0%/ c ? - 0.05%/ c absolute maximu m ratings vlcd: +0.3 to +15.0 ? - 0.3 to +17.0 dynamic current consumption idd1: 40 m a (max.) idd2: 75 m a (typ.), 100 m a (max.) 3.0 oscillator frequency (internal) 19: 22.5: 26 ? 17: 22.5: 27 oscillator frequency (external) 2.13: 2.81: 3.25 ? 2.13: 2.81: 3.37 3.1 apr.1999 4.0 change vdd range : 2.4v to 5.5v ? 2.4v to 3.6v jan.2000
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ .................. 1 features ................................ ................................ ................................ ................................ ......................... 1 block diagram ................................ ................................ ................................ ................................ .............. 3 pad configuration ................................ ................................ ................................ ................................ ....... 4 pad center coordinat es ................................ ................................ ................................ ........................... 5 pin description ................................ ................................ ................................ ................................ .............. 7 power supply ................................ ................................ ................................ ................................ ......... 7 lcd driver supply ................................ ................................ ................................ ................................ . 7 system control ................................ ................................ ................................ ................................ .... 8 microprocessor inter face ................................ ................................ ................................ .............. 9 lcd driver outputs ................................ ................................ ................................ ............................. 11 test pins ................................ ................................ ................................ ................................ .................. 11 functional descripti on ................................ ................................ ................................ ............................ 12 microprocessor inter face ................................ ................................ ................................ ............. 12 display data ram (dd ram) ................................ ................................ ................................ .................. 16 lcd display circuits ................................ ................................ ................................ ............................ 19 lcd dri ver circuit ................................ ................................ ................................ ................................ 21 power supply circuit s ................................ ................................ ................................ ....................... 22 referece circuit exa mples ................................ ................................ ................................ .............. 28 reset circuit ................................ ................................ ................................ ................................ ......... 29 instruction descript ion ................................ ................................ ................................ ........................... 30 specifications ................................ ................................ ................................ ................................ .............. 43 absolute maximum rat ings ................................ ................................ ................................ ............... 43 dc characteristics ................................ ................................ ................................ ............................. 44 reference data ................................ ................................ ................................ ................................ .... 47 ac characteristics ................................ ................................ ................................ ............................. 49 reference applicatio ns ................................ ................................ ................................ ........................... 53 microprocessor inter face ................................ ................................ ................................ ............. 53 connections between s6b0715 and lcd pane l ................................ ................................ ............ 54 tcp pin layout (samp le) ................................ ................................ ................................ ...................... 57

s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 1 introduction the s6b0715 is a driver & controller lsi for graphic dot - matrix liquid crystal display systems. it contains 33 common and 1 00 segment driver circuits. this chip is connected directly to a microprocessor, accepts serial or 8 - bit parallel displ ay data and stores in an on - chip display data ram of 65 x 1 32 bits. it provides a highly - flexible display section due to 1 - to - 1 correspondence between on - chip display data ram bits and lcd panel pixels. and it performs display data ram read/write operation with no external operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features driver output circuits - 33 common outputs / 1 00 segment outputs on - chip display data ram - capacity: 65 x 1 32 = 8 , 58 0 bits - bit data "1": a dot of display is illuminated . - bit data "0": a dot of display is not illuminated . multi - chip o peration ( m aster, s lave) a vailable appli cable duty ratios d uty ratio applicable lcd bias maximum display area 1/33 1/5 or 1/6 33 100 microprocessor interface - 8 - bit parallel bi - directional interface with 6800 - series or 8080 - series - serial interface (only write operation) available various i nstruction s etting on - chip low power analog circuit - on - chip oscillator circuit - voltage converter (x2 , x3 and x4) - voltage regulator (temperature coefficient: - 0.05%/ c , - 0. 2 %/ c) - on - chip electronic contrast control function ( 32 steps) - voltage fol lower (lcd b ias: 1/5 or 1/6) operating voltage range - supply voltage (v dd ): 2.4 to 3 . 6 v - lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 1 5 .0 v low power consumption - 100 m a typ. (v dd = 3v, x 4 boosting, v0 = 8 v, i nternal power supply on and display off) - 10 m a max. (during power save [standby] mode) wide o perating t emperature r ange - ta = - 40 c to +85 c package type - gold bumped chip or tcp
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 2 series specifications product c ode temps p in temp. c oefficient package chip t hickness s6b0715a01 - b0cz 670 m m s6b0715a01 - b0cy 0 (v ss c onne cted) - 0.05%/ c 470 m m s6b0715a11 - b0cz 670 m m s6b0715a11 - b0cy 1 (v dd c onnected) - 0.2%/ c cog 470 m m s6b0715a01 - xxx0 670 m m s6b0715a01 - xxx0 0 (v ss c onnected) - 0.05%/ c 470 m m s6b0715a11 - xxx0 670 m m s6b0715a11 - xxx0 1 (v dd c onnected) - 0.2% / c tcp 470 m m * xx: tcp ordering number
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 3 block diagram ms cl m frs disp v dd v0 v1 v2 v3 v4 v ss v0 vr te mps vout c1- c1+ c2- c2+ c3 - c 3+ v / c circuit v / r circuit v / f circuit 34 common driver circuits mpu interface (parallel & serial) instruction decoder bus holder column address circuit line address circuit page address circuit display data ram 65 x 1 32 = 8 , 58 0 bits segment controller display timing generator circuit common controller db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) mi resetb p s rw_wr e_rd r s c s2 cs1b coms com31 : : com0 coms seg99 seg98 : seg66 seg65 seg64 : seg1 seg0 oscillator i/o buffer status register instruction register testl2 1 00 segment driver circuits testl1 figure 1 . block diagram
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 4 pad configuration eee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee eee y 108 2 09 107 2 10 83 234 82 1 s 6b 071 5 (top view) (0,0) x eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eeee eeee - - - - eeee figure 2 . s6b0715 chip co nfiguration table 1 . s6b0715 pad dimensions size item pad no. x y unit chip size - 7980 2 70 0 1 to 82 90 pad pitch 83 to 234 7 0 1 to 82 5 6 11 4 83 to 1 07 108 50 1 08 to 2 09 50 108 bumped pad size 2 10 to 23 4 10 8 50 bumped pad height all pad 1 7 (typ.) m m cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m (-3832, -1055) 30 m m 30 m m 30 m m (+3832, - 1070) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (-3870, +1230) (+3870, +1230) 42 m m 108 m m
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 5 pad center coordinat es table 2 . p ad center coordinates [unit: m m] no. name x y no. name x y no. name x y 1 dummy -3645 -1226 51 c1+ 855 -1226 101 com1 3830 420 2 testl1 -3555 -1226 52 c1+ 945 -1226 102 com0 3830 490 3 vdd -3465 -1226 53 c1- 1035 -1226 103 coms 3830 560 4 frs -3375 -1226 54 c1- 1125 -1226 104 dummy 3830 630 5 m -3285 -1226 55 c2+ 1215 -1226 105 dummy 3830 700 6 cl -3195 -1226 56 c2+ 1305 -1226 106 dummy 3830 770 7 disp -3105 -1226 57 c2- 1395 -1226 107 dummy 3830 840 8 vdd -3015 -1226 58 c2- 1485 -1226 108 dummy 3535 1190 9 ms -2925 -1226 59 vss 1575 -1226 109 seg0 3465 1190 10 vss -2835 -1226 60 vss 1665 -1226 110 seg1 3395 1190 11 resetb -2745 -1226 61 vr 1755 -1226 111 seg2 3325 1190 12 vdd -2655 -1226 62 vr 1845 -1226 112 seg3 3255 1190 13 ps -2565 -1226 63 v0 1935 -1226 113 seg4 3185 1190 14 vss -2475 -1226 64 v0 2025 -1226 114 seg5 3115 1190 15 cs1b -2385 -1226 65 v0 2115 -1226 115 seg6 3045 1190 16 cs2 -2295 -1226 66 v0 2205 -1226 116 seg7 2975 1190 17 vdd -2205 -1226 67 v0 2295 -1226 117 seg8 2905 1190 18 mi -2115 -1226 68 v0 2385 -1226 118 seg9 2835 1190 19 vss -2025 -1226 69 v1 2475 -1226 119 seg10 2765 1190 20 vdd -1935 -1226 70 v1 2565 -1226 120 seg11 2695 1190 21 rs -1845 -1226 71 v2 2655 -1226 121 seg12 2625 1190 22 vss -1755 -1226 72 v2 2745 -1226 122 seg13 2555 1190 23 rw_wr -1665 -1226 73 v3 2835 -1226 123 seg14 2485 1190 24 e_rd -1575 -1226 74 v3 2925 -1226 124 seg15 2415 1190 25 vdd -1485 -1226 75 v4 3015 -1226 125 seg16 2345 1190 26 vdd -1395 -1226 76 v4 3105 -1226 126 seg17 2275 1190 27 vdd -1305 -1226 77 vss 3195 -1226 127 seg18 2205 1190 28 vdd -1215 -1226 78 vss 3285 -1226 128 seg19 2135 1190 29 vdd -1125 -1226 79 temps 3375 -1226 129 seg20 2065 1190 30 vdd -1035 -1226 80 vdd 3465 -1226 130 seg21 1995 1190 31 db0 -945 -1226 81 testl2 3555 -1226 131 seg22 1925 1190 32 db1 -855 -1226 82 dummy 3645 -1226 132 seg23 1855 1190 33 db2 -765 -1226 83 dummy 3830 -840 133 seg24 1785 1190 34 db3 -675 -1226 84 dummy 3830 -770 134 seg25 1715 1190 35 db4 -585 -1226 85 dummy 3830 -700 135 seg26 1645 1190 36 db5 -495 -1226 86 dummy 3830 -630 136 seg27 1575 1190 37 db6 -405 -1226 87 com15 3830 -560 137 seg28 1505 1190 38 db7 -315 -1226 88 com14 3830 -490 138 seg29 1435 1190 39 vss -225 -1226 89 com13 3830 -420 139 seg30 1365 1190 40 vss -135 -1226 90 com12 3830 -350 140 seg31 1295 1190 41 vss -45 -1226 91 com11 3830 -280 141 seg32 1225 1190 42 vss 45 -1226 92 com10 3830 -210 142 seg33 1155 1190 43 vss 135 -1226 93 com9 3830 -140 143 seg34 1085 1190 44 vss 225 -1226 94 com8 3830 -70 144 seg35 1015 1190 45 vout 315 -1226 95 com7 3830 0 145 seg36 945 1190 46 vout 405 -1226 96 com6 3830 70 146 seg37 875 1190 47 c3+ 495 -1226 97 com5 3830 140 147 seg38 805 1190 48 c3+ 585 -1226 98 com4 3830 210 148 seg39 735 1190 49 c3- 675 -1226 99 com3 3830 280 149 seg40 665 1190 50 c3- 765 -1226 100 com2 3830 350 150 seg41 595 1190
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 6 tab le 2 . p ad center coordinates (continued) [ u nit: m m] no. name x y no. name x y no. name x y 151 seg42 525 1190 201 seg92 -2975 1190 152 seg43 455 1190 202 seg93 -3045 1190 153 seg44 385 1190 203 seg94 -3115 1190 154 seg45 315 1190 204 seg95 -3185 1190 155 seg46 245 1190 205 seg96 -3255 1190 156 seg47 175 1190 206 seg97 -3325 1190 157 seg48 105 1190 207 seg98 -3395 1190 158 seg49 35 1190 208 seg99 -3465 1190 159 seg50 -35 1190 209 dummy -3535 1190 160 seg51 -105 1190 210 dummy -3830 840 161 seg52 -175 1190 211 dummy -3830 770 162 seg53 -245 1190 212 dummy -3830 700 163 seg54 -315 1190 213 dummy -3830 630 164 seg55 -385 1190 214 com16 -3830 560 165 seg56 -455 1190 215 com17 -3830 490 166 seg57 -525 1190 216 com18 -3830 420 167 seg58 -595 1190 217 com19 -3830 350 168 seg59 -665 1190 218 com20 -3830 280 169 seg60 -735 1190 219 com21 -3830 210 170 seg61 -805 1190 220 com22 -3830 140 171 seg62 -875 1190 221 com23 -3830 70 172 seg63 -945 1190 222 com24 -3830 0 173 seg64 -1015 1190 223 com25 -3830 -70 174 seg65 -1085 1190 224 com26 -3830 -140 175 seg66 -1155 1190 225 com27 -3830 -210 176 seg67 -1225 1190 226 com28 -3830 -280 177 seg68 -1295 1190 227 com29 -3830 -350 178 seg69 -1365 1190 228 com30 -3830 -420 179 seg70 -1435 1190 229 com31 -3830 -490 180 seg71 -1505 1190 230 coms -3830 -560 181 seg72 -1575 1190 231 dummy -3830 -630 182 seg73 -1645 1190 232 dummy -3830 -700 183 seg74 -1715 1190 233 dummy -3830 -770 184 seg75 -1785 1190 234 dummy -3830 -840 185 seg76 -1855 1190 186 seg77 -1925 1190 187 seg78 -1995 1190 188 seg79 -2065 1190 189 seg80 -2135 1190 190 seg81 -2205 1190 191 seg82 -2275 1190 192 seg83 -2345 1190 193 seg84 -2415 1190 194 seg85 -2485 1190 195 seg86 -2555 1190 196 seg87 -2625 1190 197 seg88 -2695 1190 198 seg89 -2765 1190 199 seg90 -2835 1190 200 seg91 -2905 1190
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 7 pin description power supply table 3. power s upply pin description name i/o description vdd supply power supply v ss supply ground lcd driver supply voltag es the voltage determined by lcd pixel is impedance - converted by an operational amplifier for application. voltages should have the following relationship; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd bias. lcd bias v1 v2 v3 v4 1/ 6 bias (5 / 6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/6 ) x v0 1/ 5 bias (4 / 5) x v0 (3 / 5) x v0 ( 2/ 5) x v0 ( 1/5 ) x v0 v0 v1 v2 v3 v4 i/o lcd driver supply table 4. lcd d river s upply pin description name i/o description c1 - o capacitor 1 negative connection pin for voltage converter c1+ o capacitor 1 positive connection pin for voltage converter c2 - o capacitor 2 negative connection pin for voltage converter c2+ o capacitor 2 posit ive connection pin for voltage converter c3 - o capacitor 3 negative connection pin for voltage converter c 3 + o capacitor 3 positive connection pin for voltage converter vout i/o voltage converter input / output pin vr i v0 voltage adjustment pin
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 8 syst em control table 5. system c ontrol pin description name i/o description master / slave operation select pin - ms = "h": master operation - ms = "l": slave operation the following table depends on the ms status. ms osc c ircuit power s upply c ircuit cl m frs disp h enabled input output output output output l disabled disabled input input output input ms i cl i/o display clock input / output pin when the s6b0715 is used in master/slave mode (multi - chip), the cl pins must be connected each other f or sync . m i/o lcd ac signal input / output pin when the s6b0715 is used in master/slave mode (multi - chip), the m pins must be connected each other. - ms = ? h ? : o utput - ms = ? l ? : i nput frs o static driver segment output pin this pin is used together wi th the m pin. disp i/o lcd display blanking control input/output. when s6b0715 is used in master/slave mode (multi - chip), the disp pins must be connected each other. - ms = ? h ? : o utput - ms = ? l ? : i nput temps i selects temperature coefficient of the refe rence voltage - temps = " l ": - 0.05%/ c - temps = " h ": - 0.2%/ c
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 9 microprocessor inter face table 6. microprocessor i nterface pin description name i/o description resetb i reset input pin when resetb is ?l?, initialization is executed. parallel / seri al data input select input ps interface mode chip s elect data / instruction data read / write serial clock h parallel cs1b, cs2 rs db0 to db7 e_rd rw_wr - l serial cs1b, cs2 rs sid (db7) write only sclk (db6) ps i *note: when ps is ?l?, db0 to db5 a re high impedance and e_rd and rw_wr should be fixed to either ?h? or ?l?. mi i microprocessor interface select input pin - mi = "h": 6800 - series mpu interface - mi = "l": 8080 - series mpu interface cs1b cs2 i chip select input pins data / instruction i/o is enabled only when cs1b is ?l? and cs2 is ?h?. when chip select is non - active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a. - rs = "l": db0 to db7 are control data . read / write execution control pin mi mpu type rw_wr description h 6800 - series rw read/write control input pin - rw = ?h?: read - rw = ?l?: write l 8080 - series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw_wr i
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 10 table 6. microprocessor i nterface pin description (continued) name i/o description read / write execution control pin mi mpu type e_rd description h 6800 - series e read / write control input pin - rw = ?h?: when e is ? h?, db0 to db7 are in an output status. - rw = ?l?: the data on db0 to db7 are latched at the falling edge of the e signal. l 8080 - series /rd read enable clock input pin when /rd is ?l?, db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8 - bit bi - d irectional data bus that is connected to the standard 8 - bit microprocessor data bus. when the serial interface selected (ps = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active , db0 to db7 may be high impedance.
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 11 lcd driver outputs table 8. lcd d river o utputs pin description name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss v ss seg 0 to seg 99 o lcd common driver outputs the internal scanning data and m signal control the ou tput voltage of common driver. scan data m common driver output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss com 0 to com 31 o coms o common output for the icons the output signals of two pins are same. when not used, these pins should be left open. i n multi - chip (master/slave) mode, all coms pins on both master and slave units are the same signal. test pins table 8. test pin description name i/o description testl1 testl2 i ic test pins with pull - up these pins must be open . note: dummy ? these pins should be opened (floated).
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 12 functional descripti on microprocessor inter face chip select input there are cs1b and cs2 pins for c hip s election. the s6b0715 can interface with an mpu only when cs1b is ?l? and cs2 is ?h?. when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface s6b0715 has three types of inter face with an mpu, which are one serial and two parallel interface. this parallel or serial interface is determined by ps pin as shown in table 9 . table 9 . parallel / serial interface mode ps type cs1b cs2 mi interface mode h 6800 - seri es mpu mode h parallel cs1b cs2 l 8080 - series mpu mode l serial cs1b cs2 * serial - mode * : don't care parallel interface (ps = "h") the 8 - bit bi - directional data bus is used in parallel interface and the type of mpu is selected by mi as shown in table 10 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 11 . table 10 . microprocessor selection for parallel interface mi cs1b cs2 rs e_rd rw_wr db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800 - series l cs1b cs2 rs /rd /wr db0 to db7 8080 - series table 11 . parallel data transfer common 6800 - series 8080 - series rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) description h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l write s to internal register (instruction)
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 13 serial interface (ps = "l") when the s6b0715 is active, serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8 - bit shift register and the 3 - bit counter are reset. serial data can b e read on the rising edge of serial clock going into db6 and processed as 8 - bit parallel data on the eighth serial clock. serial data input is display data when rs is high and control data when rs is low. since the clock signal ( db6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. cs1b cs2 sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . serial interface timing busy flag the b usy f lag indicates whether the s6b0715 is oper ating or not. when db7 is ?h? in r ead s tatus operation, this device is in busy status and will accept only r ead s tatus instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mp u performance.
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 14 data transfer the s6b0715 uses bus holder and internal data bus for d ata t ransfer with the mpu. when writing data from the mpu to on - chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 4 . and when r eading data from on - chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 5 . this means that a dummy read cycle m ust be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the secon d read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 4 . write timing
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 15 rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 figure 5 . read timing
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 16 display data ram (dd ram) the display data ram stores pixel data for the lcd. it is 65 - ro w by 1 32 - column addressable array. each pixel can be selected when the page and column addresses are specified. the 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (db0 only). data is read from or written to the 8 lines of e ach page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 6. the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operate s independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. com 0 - - com 1 - - com 2 - - com 3 - - com 4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 d isplay d ata ram lcd display figure 6 . ram - to - lcd data transfer page address circuit this circuit is for prov iding a page address to display data ram shown in figure 8 . it incorporates 4 - bit p age a ddress register changed by only the ?set page? instruction. page a ddress 8 (db3 is ?h?, but db2, db1 and db0 are ?l?) is a special ram area for the icons and display da ta db0 is only valid. when page address is above 8, it is impossible to access to on - chip ram. line address circuit this circuit assigns ddram a l ine a ddress corresponding to the first line (com 0 ) of the display. therefore, by setting l ine a ddress repeated ly, it is possible to realize the screen scrolling and page switching without changing the contents of on - chip ram as shown in figure 8 . it incorporates 6 - bit line address register changed by only the in itial d isplay l ine instruction and 6 - bit counter circ uit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by cl signal and generates the l ine a ddress for transferring the 1 32 - bit ram data to the 100 d isplay data latch circuit. however, display da ta of icons are not scrolled because the mpu can not access l ine a ddress of icons.
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 17 column address circuit column a ddress circuit has an 8 - bit preset counter that provides column address to the display data ram as shown in f igure 8 . when set column address msb / lsb instruction is issued, 8 - bit [y 7 :y0] is updated. and, since this address is increased by 1 each a r ead or w rite data instruction, microprocessor can access the display data continuously. however, the counter is not incre as ed and locked if a non - existing address above 84 h. it is unlocked if a column address is set again by set column address msb / lsb instruction. and t he column address counter is independent of page address register. adc s elect instruction makes it possible to invert the relation ship between the column address and the segment outputs. it is necessary to rewrite the display data on built - in ram after issuing adc s elect instruction. refer to the following figure 7 . seg output - seg 0 seg 1 seg 2 ... ... seg 97 seg 98 seg 99 - colum n address [y 7 :y0] 00h~ 0fh 10h 01h 02h ... ... 71 h 72 h 73h 74h~ 83 h display data 1 0 0 0 1 1 0 lcd panel display ( adc = 0 ) not outputted ... ... not outputted lcd panel display ( adc = 1 ) not outputted ... ... not outputted figure 7 . the relationship b etween t he column address a nd t he segment outputs segment control circuit this circuit controls the display data by the display on / off, r everse d isplay on / off and e ntire d isplay on / off instructions witho ut changing the data in the display data ram.
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 18 page0 page2 page1 page4 page3 page6 page5 page7 page8 line address com output page address db3 db0 db1 db2 data - - - - - - - - - - - - - - - seg99 seg98 seg97 - seg0 seg1 seg2 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 28h 27h 26h 25h 24h 23h 22h 21h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 38h 37h 36h 35h 34h 33h 32h 31h 39h 3ah 3bh 3ch 3dh 3eh 3fh - - - - - - - - - - - - - - - - - - - - - com1 com0 - - - - - - - com2 com11 com10 com9 com8 com7 com5 com6 com4 com3 com12 com21 com20 com19 com18 com17 com15 com16 com14 com13 com22 com31 com30 com29 com28 com27 com25 com26 com24 com23 - - coms - - 83 start initial start line address = 1ch - 74 72 73 71 00 - 0f 11 10 12 12 11 10 - 1f 00 71 72 73 - 74 83 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 figure 8 . display data ram map
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 19 lcd display circuits oscillator this is completely on - chip o scillator and its frequency is nearly independent of v dd . this oscillator signal is used in the voltage converter and display timing generation circuit. * test c ondition: temperature: 25 c & 85 c, temps = ? l ? , no l oad v dd vs. fosc 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] fosc [khz] 1/33 duty (25 c ) 1/33 duty (85 c ) figure 9 . v dd vs. f osc display timing generator circuit this circuit gen erates some signals to be used for displaying lcd. the display clock, cl, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on - chip ram is generated in synchronization wi th the display clock (cl) and the 1 00 - bit display data is latched by the display data latch circuit in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ra m from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. driving 2 - frame ac driver wavef orm and internal timing signal are shown in figure 10 . in a multi ple - chip configuration , the slave chip requires the m , cl and disp signals from the master. t able 12 shows the m, cl, and disp status. table 12 . master and slave timing signal status operatio n mode oscillator m cl disp on (internal clock used) output output output master off (external clock used) output input output slave - input input input
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 20 m com0 v0 v1 v2 v3 v4 v ss com1 v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss segn 32 33 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 32 33 1 2 3 4 5 6 cl figure 9 . 2 - frame ac driving waveform com mon output control circuit this circuit controls the relationship between the number of common output and specified duty ratio. shl select instruction specifies the scanning direction of the common output pins . table 13. the relationship between duty rati o and common output common o utput p ins duty shl com0 to com31 coms 0 com0 to com31 1/33 1 com31 to com0 coms
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 21 lcd driver circuit this driver circuit is configured by 34 - c hannel (including 2 coms channel) common driver and 1 00 - channel segment drive r. this lcd panel driver voltage depends on the combination of display data and m signal. com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com1 0 com1 1 com1 2 com1 3 com1 4 com 15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg 2 seg 1 seg 0 com 2 com 0 com 1 m v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v dd v ss figure 10 . segment and common timing
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 22 power supply circuit s the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low - power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and controlled by power control instruction. for details, refers to "instruction description". table 14 shows the referenced combinations in using p ower s upply circuits. table 14 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/ r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on open external input open only the external power supply circuits are used 0 0 0 off off off open external input external input
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 23 voltage converter circuits these circuits boost up the electric potential between v dd and v ss to 2, 3, or 4 times toward positive side and boosted voltage is outputted from vout pin. [c1 = 1.0 to 4.7 m f] vout = 2 v dd vout c3+ c3 - c2+ c2 - c1+ c1 - v dd v dd v ss - + - + c1 c1 gnd v ss v dd vout = 3 v dd v dd v ss v dd - + + - - + c1 c1 c1 gnd v ss v dd vout c3+ c3 - c2+ c2 - c1+ c1 - figure 11 . two times boosting circuit figure 12 . three times boosting circuit vout = 4 v dd v dd v dd v ss - - + + - + - + c1 c1 c1 c1 gnd v ss v dd vout c3+ c3 - c2+ c2 - c1+ c1 - figure 13 . four times boosting circuit
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 24 voltage regulator circuits the function of the internal v oltage r egulator circuits is to determine liquid c rystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational - amplifier circuits shown in f igure 14 , it is necessary to be applied internally or externally. for the eq. 1 , we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 31 . v ref voltage at ta = 25 c is shown in t able 15 - 1 . rb v0 = ( 1 + ? ? ? ? ) x v ev [v] ------ (eq. 1) ra ( 31 - a ) v ev = ( 1 - ? ? ? ? ? ? ) x v ref [v] ------ (eq. 2) 15 0 table 15 - 1. v ref v oltage at ta = 25 c temps temp. coefficient v ref [v] l - 0.05% / c 1 . 9 h - 0. 2 % / c 2.1 table 15 - 2. reference voltage parameter ( a ) s v4 s v3 s v2 s v1 s v0 reference voltage p arameter ( a ) 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : 1 1 1 1 0 30 1 1 1 1 1 31
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 25 v ev gnd ra rb v ss vr v0 vout + - figure 14 . internal v oltage r egulator c ircuit
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 26 in case of using external resistors, ra and rb i t is necessary to connect external regulator resis tor ra between vr and v ss , and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 8 v 2. 5 - bit reference voltage register = (1, 1 , 1 , 1 , 1 ) 3. m aximum current flowing ra, rb = 1 ua from eq. 1 rb 8 = ( 1 + ? ? ? ) x v ev [v] ------ (eq. 3) ra from eq. 2 ( 31 - 3 1 ) v ev = ( 1 - ? ? ? ? ? ? ) x 1.9 = 1.9 [v] ------ (eq. 4) 150 from requirement 3. 8 ? ? ? ? ? ? = 1 [ua] ------ (e q. 5) ra + rb from equations eq. 3, 4 and 5 ra = 1.9 [m w ] rb = 6 .1 [m w ] the following table shows the range of v0 depending on the above requirements. table 16. v0 depending on electronic volume l evel electronic volume level 0 ....... 16 ....... 31 v0 6.33 ....... 7.19 ....... 8
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 27 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4) and those output impedance are converted by the v oltage f ollower for increasing drive capability . table 17 shows the relationship between v1 to v4 level and bias . table 17. t he r elationship between v1 to v4 l evel and bias duty r atio lcd bias v1 v2 v3 v4 1/6 (5/6) x v0 (4 / 6) x v0 ( 2/ 6) x v0 ( 1/ 6) x v0 1/33 1/5 (4/5) x v0 (3 / 5) x v0 ( 2/ 5) x v0 ( 1/ 5) x v0
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 28 referece circuit exa mples v dd ms v ss c1 ra rb c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c1 c1 c1 v dd ms v ss ra rb c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 external power supply figure 15. when using al l lcd power circuits figure 16. when not u sing v/c c ircuit (4 - t ime v/c: o n , v/r: on , v/f: o n ) v dd ms v ss v dd ms v ss external power supply external power supply c2 - + c2 - + c2 - + c2 - + c2 - + vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 vout c3+ c3- c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 value of external capacitance item value unit c1 1.0 to 4.7 c2 0.47 to 1.0 m f figure 17. when using s ome lcd power circuits figure 18. when not u sing i nternal (v/c: o ff , v/r: o ff , v/f: o n ) lcd power supply c ircuit
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 29 reset circuit s etting resetb to ?l? or reset instruction can initialize internal function. when resetb becomes ?l?, following procedure is occurred. display on / off: off entire display on / off: off (normal) adc select: off (normal) reverse display on / off: off (norma l) power control register (vc, vr, vf) = (0, 0, 0) lcd bias ratio: 1/6 r ead - m odify - write : off shl select: off (normal) static indicator mode: off d isplay start line: 0 (first) column address: 0 page address: 0 reference voltage set: off reference voltage c ontrol register: ( s v4, s v3, s v2, s v1, s v0) = (0, 0, 0, 0, 0) when reset instruction is issued, following procedure is occurred. r ead - m odify - write : off static indicator mode: off shl select: 0 d isplay start line: 0 (first) column address: 0 page address: 0 reference voltage set: off reference voltage control register: ( s v4, s v3, s v2, s v1, s v0) = (0, 0, 0, 0, 0) while resetb is ?l? or r eset instruction is executed, no instruction except read status c ould be accepted. reset status appears at db4. after db4 becomes ?l?, any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 30 instruction descript ion table 18 . instruction table : don?t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy adc on /off res etb 0 0 0 0 read the inter nal status display on / off 0 0 1 0 1 0 1 1 1 d on turn on / off lcd panel when d on = 0: display off when d on = 1: display on initial display line 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 specify ddram line for com0 set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 set r eference v oltage m ode set r eference v oltage r egister 0 0 1 0 0 s v4 s v3 s v2 s v1 s v0 set r eference v oltage r egister set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 0 y6 y5 y4 set column address msb set co lumn address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb adc select 0 0 1 0 1 0 0 0 0 adc select seg output direction when adc = 0 : normal direction (seg0 ? seg99) when a dc = 1 : reverse direction (seg99 ? seg0) reverse display on / off 0 0 1 0 1 0 0 1 1 rev select normal / reverse display when rev = 0 : normal display when rev = 1 : reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon select normal/ entire display on when eon = 0 : normal display. when eon = 1 : entire display on lcd bias select 0 0 1 0 1 0 0 0 1 bias select lcd bias set modify - read 0 0 1 1 1 0 0 0 0 0 set modify - read mode reset modify - read 0 0 1 1 1 0 1 1 1 0 release modify - read mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions shl select 0 0 1 1 0 0 sh l select com output direction when shl = 0 : normal direction (com0 ? com31) when shl = 1: reverse direction (com31 ? com0) power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation set static indicator r egister 0 0 1 0 1 0 1 1 0 s i set static indicator register si = 0 (off), si = 1 (on) power s ave - - - - - - - - - - compound instruction of display off and entire display on test instruction 0 0 1 1 1 1 don't use this instruction.
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 31 read display data 8 - bit data from d isplay d ata ram specified by the column address and page address c ould be read by this instruction. as the column address is incre as ed by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8 - bit data of display data from the micropr ocessor can be written to the ram location specified by the column address and page address. the column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data data write set column address set page address optional status column = column + 1 no yes data write continue ? dummy data read set column address set page address optional status column = column + 1 no yes data read continue ? data read column = column + 1 figure 19 . sequence for writing display data figure 20 . sequence for reading display data
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 32 read status indicates the internal status of the s6b0715 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on / off res etb 0 0 0 0 flag description busy the device is busy when internal operation or reset any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy. adc indicates the relationship between ram c olumn address and segment driver. 0: reverse direction (seg 99 ? seg 0 ), 1: normal direction (seg 0 ? seg 99 ) on / off indicates display on / off status 0: display on, 1: display off res etb indicates the initialization is in progress by resetb signal 0: chip is active, 1: chip is being reset display on / off turns the display on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d on d on = 1: display on d on = 0: display off initial display line sets the line address of display ram to determine the i nitial d isplay l ine . the ram display data is displayed at the top row (com 0 when shl = l, com31 when shl = h ) of lcd panel. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 s t 5 s t 4 s t 3 s t 2 s t 1 s t 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 33 reference voltage select consists of 2 - byte instruction the 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. after second instru ction, reference voltage m ode is released. the 1 st instruction : set reference voltage select m ode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction : set reference voltage r egister rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 s v4 s v3 s v2 s v1 s v0 s v4 s v3 s v2 s v1 s v0 reference voltage pa rameter ( a ) 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : 1 1 1 1 0 30 1 1 1 1 1 31 2 nd instruction for register setting setting r eference v oltage end 1 st instruction for mode setting setting r eference v oltage start figure 21 . sequence for setting the r eference v oltage
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 34 set page addre ss sets the p age a ddress of display data ram from the microprocessor into the p age a ddress register. any ram data bit can be accessed when its p age a ddress and column address are specified. along with the column address, the p age a ddress defines the addres s of the display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 p age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 s et column address sets the c olumn a ddress of display ram from the microprocessor into the column address register. along with the c olumn a ddress, the c olumn a ddress defines the address of the display ram to write or read display data. when the microprocess or reads or writes display data to or from display ram, c olumn a ddresses are automatically incre as ed. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y6 y5 y4 y3 y2 y1 y0 c olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 0 1 0 98 1 1 0 0 0 1 1 99
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 35 adc select changes the relationship between ram column address and segment driver. the direction of segment dri ver output pins c ould be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg 0 ? seg 99 ) adc = 1: reverse direction (seg 99 ? seg 0 ) reverse di splay on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ?1? ram bit data = ?0? 0 (normal) lcd pixel is illuminated lc d pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated reverse display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the displa y data ram are held. this instruction has priority over the r everse d isplay o n / o ff instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon = 0: normal di splay eon = 1: e ntire d isplay o n select lcd bias selects lcd bias ratio of t he voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 bias lcd bias d uty r atio b ias = 0 b ias = 1 1/33 1/ 6 1/5
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 36 set modify - r ead this instruction stops the automatic increment of the column address by the r ead d isplay d ata instruction, but the column address is still increased by the w rite di splay d ata instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is c anceled by the r eset modify - r ead instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify - r ead this instruction cancels the modify - read mode, and makes the column address return to its initial value just before the s et modify - r ead instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess no yes change c omplete ? set column address (n) dummy r ead data r ead data w rite return c olumn a ddress (n) figure 22 . sequence for cursor display
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 37 reset this instruction r esets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply , which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0 shl s elect com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl : don ? t care shl = 0: normal direction (com 0 ? com 31 ) shl = 1: r everse direction (com 31 ? com 0 ) power control selects one of eight power circuit functions by using 3 - bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on set static indicator state this instruction sets the static indicator on / off. when it is on, the st atic indicator operates and blinks at an interval of approximately 1second. set static indicator register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 s i s i status of static indicator output 0 off 1 on (about 1 second blinking)
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 38 power save ( compound instruction ) if the entire display on / off instruction is issued during the display off state, s6b0715 enters the p ower s ave status to reduce the power consumption to the static power consumption value. according to the status of static indicat or mode, p ower s ave is entered to one of two modes (sleep and standby mode). when s tatic i ndicator mode is on, standby mode is issued, when off, sleep mode is issued. power save mode is released by the display on & entire display off instruction. release standby mode power save off (compound instruction) [entire display off] [display on] release sleep mode power save off (compound instruction) [entire display off] [static indicator on] [display on] power save (compound instruction) [display off] [entire display on] static indicator off static indicator o n sleep mode [oscillator c ircuit: off] [lcd power s upply c ircuit: off] [all com / seg o utputs: v ss ] [consumption c urrent: < 2 m a] standby mode [oscillator c ircuit: on] [lcd power s upply c ircuit: off] [all com / seg o utputs: v ss ] [consumption c urrent: < 10 m a] figure 23 . power save routine
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 39 r eferential instruction setup flow (1) end of initialization waiting for stabilizing the lcd power levels user application setup by internal instructions [adc select] [shl select] [lcd bias select] start of initialization resetb pin = ? h ? waiting for stabilizing the power power o n (v dd - v ss ) keeping the resetb pin = ? l ? user system setup by external pins user lcd p ower setup by internal instructions [voltage converter on] user lcd p ower setup by internal instructions [voltage regulator on] user lcd p ower setup by internal instructions [voltage follower on] waiting for 3 1ms waiting for 3 1ms user lcd p ower setup by internal instructions [reference voltage r egister s et] figure 24 . initializing with the b uilt - in p ower s upply c ircuits
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 40 r eferential instruction setup flow (2) user application setup by internal instructions [adc select] [shl select] [lcd bias select] start of initialization resetb pin = ? h ? waiting for stabilizing the power power o n (v dd - v ss ) keeping the resetb pin = ? l ? user system setup by external pins set power save release power save user lcd p ower setup by internal instructions [reference voltage r egister s et] waiting for stabilizing the lcd power levels end of initialization figur e 25 . initializing without the b uilt - in p ower s upply c ircuits
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 41 r eferential instruction setup flow (3) end of initialization write display on / off by instruction [display o n / off] display data ram addressing by instruction [initial display line] [set page address] [set column address] end of data display turn display on / off by instruction [display o n / o ff ] figure 26 . data d isplaying
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 42 r eferential instruction setup flow (4) turn display on / off by instruction [display o ff ] optional status power off (v dd -v ss ) user lcd power setup by internal instructions [voltage follower o ff ] user lcd power setup by internal instructions [voltage regulator o ff ] user lcd power setup by internal instructions [voltage converter o ff ] waiting for 3 50ms waiting for 3 1ms waiting for 3 1ms figure 27 . power off
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 43 spec ifications absolute maximum rat ings table 19. absolute maximum ratings parameter symbol rating unit v dd - 0.3 to +7.0 v supply voltage range v lcd - 0.3 to + 17 .0 v input voltage range v in - 0.3 to v dd +0.3 v operating temperature range t opr - 40 to +85 c storage temperature range t str - 55 to +125 c notes: 1. vdd and vlcd are based on v ss = 0v. 2. voltages v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. (vlcd = v0 ? vss) 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 44 dc characteristics table 20. dc characteristics ( v ss = 0v, v dd = 2.4 to 3 .6v, ta = - 40 to 85 c ) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 2.4 - 3 .6 v vdd *1 operating voltage (2) v0 4.0 - 1 5 .0 v v0 *2 high v ih 0.8v dd - v dd input voltage low v il v ss - 0.2 v dd v *3 high v oh i oh = - 0.5ma 0.8v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0.2v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a * 5 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a * 6 lcd driver on resistance r o n ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn * 7 internal f osc 17 22.5 27 oscillator frequency (1) external f cl ta = 25 c 2.13 2.81 3.37 khz cl *8 2 2.4 - 3.6 3 2.4 - 3.6 voltage converter input voltage v dd 4 2.4 - 3. 6 v v dd volta ge converter output voltage v out 2 / 3 / 4 voltage conversion (no - load ) 95 99 - % vout voltage regulator operating voltage v out 4 .0 - 1 5 .0 v vout voltage follower operating voltage v0 4.0 - 1 5 .0 v v0 * 9 v ref 0 - 0.05%/ c 1. 8 4 1.9 1.96 v * 10 reference voltage v ref 1 ta = 25 c - 0.2%/ c 2 . 0 4 2. 1 2. 1 6 v * 10
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 45 dynamic current consumption (1): when the b uilt - in power c ircuit is off (at o perate m ode) (ta = 25 c ) item symbol condition min. typ. max. unit pin used dynamic current consumption (1) i dd1 v d d = 3.0v v0 ? v ss = 8.0v display off, c hecker p attern - 5 20 m a *11 dynamic current consumption (2): when t he built - in power circuit is on (at operate mode) (ta = 25 c ) item symbol condition min. typ. max. unit pin used v dd = 3.0v, quad boosting, v0 ? v ss = 8 .0v, 1/65 duty ratio, display off, c hecker pattern normal power mode - 47 70 dynamic current consumption (2) i dd2 v dd = 3.0v, quad boosting, v0 ? v ss = 8 .0v, display on, checker pattern normal power mode - 75 100 m a *1 2 current consumption during power save mode (ta = 25 c ) item symbol condition min. typ. max. unit pin used sleep mode i dds1 during s leep - - 2.0 m a standby mode i dd s 2 during s tandby - - 10.0 m a
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 46 table 21 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f m on - chip oscillator circuit is used f osc ? ? ? ? 8 f osc ? ? ? ? 16 33 1/33 on - chip oscillator circuit is not used external input (f cl ) f osc ? ? ? ? 2 33 (f osc : oscillation frequency, f cl : display clock frequency, f m : lcd ac sig nal frequency ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . cs1b, cs2, rs, db 0 to db7, e_rd, rw_wr, resetb, ms, mi , ps, temps , cl, m, disp pins . *4 . db0 to db7, m , frs, disp, cl pins . *5 . cs1b, cs2, rs, db[7:0], e_rd, rw_wr, resetb, ms, mi, ps, temps, cl, m, disp pins. *6 . applies when the db[7:0], m, disp, and cl pins are in high impedance. *7 . resistance value when 0.1[ma] is applied during the on status of the output pin segn or comn. ron= d v / 0.1 [k w ] ( d v: voltage change when 0.1[ma] is applied in the on status.) *8 . see table 21 for the relationship between oscillatio n frequency and frame frequency. *9 . the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range . *10 . on - chip reference voltage source of the voltage regulator circuit to adjust v0. *11,12. applies to the case where the on - chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built - in power supply circuit is on or off. the current flowing through voltage regulation resistors (ra and rb) is not include d. it does not include the current of the lcd panel capacity, wiring capacity, etc.
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 47 reference data idd1 vs. v dd l test c ondition: temperature ( 25 c & 85 c ) , v0 = 8v (external), temps = 'l', 1/33 duty, ra = 1 [ m w ] , rb = 3 [ m w ] , normal power mode v dd vs. i dd1 (pattern off) 0.00 2.00 4.00 6.00 8.00 10.00 12.00 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] i dd1 [ua] 8.0v, 1/33 duty (25c) 8.0v, 1/33 duty (85c) figure 28. display pattern is o ff
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 48 i dd2 vs. v dd l test c ondition: temperature ( 25 c & 85 c ) , quad boosting, rr = 6, ev = 32 , te mps = 'l', 1/33 duty, ra = 1 [ m w ] , rb = 3 [ m w ], normal power mode v dd vs. i dd2 (pattern off) 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] i dd2 [ua] 1/33 duty (25c) 1/33 duty (85c) figure 29. display pattern is o ff v dd vs. i dd2 (checker pattern) 0.00 50.00 100.00 150.00 200.00 250.00 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5 v dd [v] i dd2 [ua] 1/33 duty (25 c ) 1/33 duty (85 c ) figure 30. display pattern is checker
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 49 ac characteristics read / write characteristics (8080 - series mpu) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw80(r) , t pw80(w) t cy80 t ah80 t as80 db 0 to db 7 (write) db 6 to db 7 (read) rd, wr cs1b (cs2 = 1) rs fig ure 31. read / write characteristics (8080 - series mpu) (v dd = 2.4 to 3. 6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time rs t as80 t ah80 13 17 - - ns system cycle time rs t cy80 400 - - ns pulse wi dth (wr) rw_wr t pw80(w) 55 - - ns pulse width (rd) e_rd t pw80(r) 125 - - ns data setup time data hold time t ds80 t dh80 35 13 - - ns read access time output disable time db7 to db0 t acc80 t od80 - 10 - 125 90 ns c l = 100 pf
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 50 read / write characteris tics (6800 - series microprocessor) t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t pw68(r) , t pw68(w) t cy68 t ah68 t as68 db 0 to db 7 (write) e cs1b (cs2 = 1) rs db 0 to db 7 (read) figure 32. read / write characteristics (6800 - series microprocessor) (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark address setup time address hold time r s t as68 t ah68 13 17 - - ns system cycle time rs t cy68 400 - - ns data setup time data hold time t ds68 t dh68 35 13 - - ns access time output disable time db7 to db0 t acc68 t od68 - 10 - 125 90 ns c l = 100 pf enable pulse width read write e_rd t pw68(r ) t pw68(w) 125 55 - - -
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 51 serial interface characteristics db7 (sid) db6 (sclk) rs cs1b (cs2 = 1) t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 33. serial interface characteristics (v dd = 2.4 to 3 . 6 v, ta = - 40 to +85 c ) item signal symbol min typ max unit remark serial clock cycle sclk high pulse w idth sclk low pulse width db6 (sclk) t cys t whs t wls 4 50 1 8 0 1 35 - - - - - - ns address setup time address hold time rs t ass t ahs 90 360 - - - - ns data setup time data hold time db7 (sid) t dss t dhs 90 9 0 - - - - ns cs1b setup time cs1b hold time cs1b t css t chs 5 5 1 8 0 - - - - ns
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 52 reset input timing resetb t rw figure 34. reset input timing (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark reset low pulse width resetb t rw 9 00 - - ns display co ntrol output timing t dm cl m figure 35. display control output timing (v dd = 2.4 to 3.6 v, ta = - 40 to +85 c) item signal symbol min. typ . max. unit remark m d elay t ime m t dm - 13 70 ns
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 53 reference applicatio ns microprocessor inter fac e in case of interfaci ng with 6800 - series (ps = ?h?, mi = ?h?) db0 to db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb mi ps ks07 15 figure 36. i nterfacing with 6800 - series (ps = ?h?, mi = ?h?) in case of interfacing with 8080 - series (ps = ?h?, mi = ?l?) db0 to db7 resetb v dd v ss /wr /rd rs cs2 cs1b 8080-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb mi ps s 6b 071 5 figure 37. i nte rfacing with 8080 - series (ps = ?h?, mi = ?l?) in case of serial interface (ps = ?l?, mi = ?h/l?) open resetb v ss v dd or v ss sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 mi ps s 6b 071 5 figure 38. s erial i nterface (ps = ?l?, mi = ?h/l?)
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 54 connections between s6b0715 and lcd pane l single chip configuration (1/ 33 duty c onfigurations) com 15 : com 0 coms coms com 3 1 : com 16 seg 99 ........... seg 0 s 6b 071 5 ( bottom view) com 15 : com 0 coms coms com 3 1 : com 16 seg 0 ............ seg 99 s 6b 071 5 ( top view) ? a x a ? a x a 32 1 00 pixels ? a x a ? a x a 32 1 00 pixels figure 39 . shl = 0, adc = 1 figure 40 . shl = 0, adc = 0 co m s com 0 : co m15 co m16 : com 3 1 com s se g99 ........... se g0 s 6b 071 5 ( top view) 32 1 00 pixels com 16 : com 3 1 coms coms com 0 : com 15 seg 0 ........... seg 99 s 6b 071 5 ( bottom view) 32 1 00 pixels ? a x a ? a x a ? a x a ? a x a figure 41 . shl = 1, adc = 0 figure 42 . shl = 1, adc = 1
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 55 mu l ti ple c hip configuration - 33com (32com + 1coms) 200seg ( 1 00seg 2) com 15 : com 0 coms coms com 31 : com 16 seg 99 ................... seg 0 s 6b 071 5 ( bottom view ) ( master ) com 15 : com 0 coms coms com 3 1 : com 16 seg 99 ................... seg 0 s 6b 071 5 ( bottom view ) ( slave ) ? a x a ? a x a 32 2 00 pixels figure 43 . shl = 0, adc = 1 connect the following pins of two chips each other - displ ay clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4 ? a x a ? a x a 32 2 00 pixels com 16 : com 3 1 coms coms com 0 : com 15 seg 0 ............... seg 99 s 6b 071 5 ( bottom view ) ( master ) com 16 : com 3 1 coms coms com 0 : com 15 seg 0 ............... seg 99 s 6b 071 5 ( bottom view ) ( slave ) figure 44 . shl = 1, adc = 0 connect the following pins of two chips each other - display clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4
33 com / 1 00 seg driver & contro ller for stn lcd s6 b0715 56 - 66com (64com + 2coms) 100seg coms com 0 : com 15 com 16 : com 3 1 coms seg 99 ................... seg 0 s 6b 071 5 ( top view ) ( slave ) com s com 31 : com 16 com 15 : com 0 com s seg 0 ................... seg 99 s 6b 071 5 ( top view ) ( master ) ? a x a ? a x a 64 1 00 pixels figure 45. 66com (64com + 2coms) 100seg connect the following pins of two chips each other - display clock pins: cl, m - display c ontrol pin: disp - lcd power pins: v0, v1, v2, v3, v4 common / segment output direction select - master c hip: shl = 0, adc = 0 - slave c hip: shl = 1, adc = 1
s6b0715 33 com / 1 00 seg driver & contro ller for stn lcd 57 tcp pin layout (samp le) s6b0715 (top view) frs m cl disp ms resetb ps cs1b cs2 mi rs rw_wr e_rd v dd db0 db1 db2 db3 db4 db5 db6 db7 v ss vout c3+ c3- c1+ c1- c2+ c2- v ss vr v0 v1 v2 v3 v4 v ss temps com s com3 1 com3 0 : : : com 2 6 com 25 com 24 : : : com 19 com 18 com 17 com 16 seg 99 seg 98 seg 97 seg 96 : : : : seg66 seg65 seg64 seg63 : : : : seg 3 seg 2 seg 1 seg 0 com s com 0 com 1 : : : com 7 com 8 com 9 : : : com 1 3 com 14 com 15 coms figure 46. tcp pin layout

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